It is known that optical lithography has reached the end of its capability at the 193 nm light wavelength and 1.35 numerical aperture (NA) immersion system. The minimum straight line resolution capability of this equipment is approximately 40 nm with an approximate 80 nm feature-to-feature pitch. A feature-to-feature pitch requirement lower than about 80 nm would require multiple patterning steps for a given structure type within a given chip level. Also, line end resolution becomes more challenging as lithography is pushed toward its resolution limits. In semiconductor device layout, a typical metal line pitch at the 32 nm critical dimension is approximately 100 nm. In order to achieve the cost benefit of feature scaling, a scaling factor of 0.7 to 0.75 is desirable. The scaling factor of about 0.75 to reach the 22 nm critical dimension would require a metal line pitch of about 75 nm, which is below the capability of current single exposure lithography systems and technology. It is within this context that the present invention arises.